1. Field of the Invention
The present disclosure generally relates to integrated circuits, and, more particularly, to circuit elements and capacitors engineered in accordance with advanced CMOS techniques in which antiferroelectric high-k materials are applied.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes ranging even into the deep sub-micron regime, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 10 nm. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than discrete circuits composed of independent circuit components. The majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors) and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area. Typically, present-day integrated circuits involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a MOSFET is that of an electronic switching element, wherein a current through a channel between source and drain of a MOSFET is controlled by a gate to which a voltage relative to source and drain is applied. Particularly, in applying a voltage exceeding a characteristic voltage level, the conductivity state of a MOSFET is changed by the voltage being applied to the gate passing a certain voltage value. The characteristic voltage level, usually referred to as threshold voltage (Vt), characterizes the switching behavior of a MOSFET. In general, Vt depends nontrivially on the transistor's properties, such as material, etc.
It is well known that conventional MOSFETs require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10 (also referred to as subthreshold swing). This minimum subthreshold swing puts a fundamental lower limit on the operating voltage and, hence, on the power dissipation in standard MOSFET-based switches. In Salahuddin et al., Nanolett. 8, 405 (2008), it was suggested to replace the gate oxide of a FET with a ferroelectric insulating material of a thickness smaller than a critical thickness in order to implement a step-up voltage transformer amplifying the gate voltage. This suggestion was based on the theoretical observation that the ferroelectric insulating material having a thickness smaller than the critical thickness provides a capacitor with an effective negative capacitance arising from an internal positive feedback, offering a possibility to further reduce the subthreshold swing. In the publication Khan et al., “Ferroelectric Negative Capacitance MOSFET: Capacitance Tuning & Antiferroelectric Operation,” IEDM (2011), a design methodology of ferroelectric negative capacitance FETs (NCFETs) was presented, wherein a high-k gate oxide of a MOSFET device was combined with a ferroelectric dielectric layer formed thereon. The thickness of the ferroelectric material was selected so as to result in a negative capacitance of about the same magnitude about compensating the capacitances in the MOSFET device, stabilizing the MOSFET with negative capacitance (NCFET=negative capacitance FET) and effectively increasing the resulting gate capacitance which enabled sub-60 mV/dec operation. A metal layer was disposed between the ferroelectric dielectric layer and the high-k gate oxide for averaging out charge non-uniformities due to domain formation in the ferroelectric dielectric. Khan et al.
suggested designing the hysteresis loop of NCFETs having antiferroelectric characteristics within the VDD window.
Besides MOSFETs, typical integrated circuits may further have capacitors and resistors implemented as so-called integrated passive devices (IPDs) or integrated passive components (IPCs) for forming functional blocks, such as impedance-matching circuits, harmonic filters, couplers etc. IPDs or IPCs can be generally fabricated using standard semiconductor manufacturing technologies which are well known in the fabrication of MOSFETs. Capacitors may be implemented by means of metal insulator semiconductor structures (MIS structures) or metal insulator metal structures (MIM structures) having a metal layer formed on an insulating material, which in turn is disposed on a semiconductor material in MIS structures or on a metal layer in MIM structures. Typical applications of MIS/MIM capacitors concern power supply buffering, RF decoupling or boost converters.
In improving ICs, it turned out that capacitors having higher capacitance are required for enabling a greater amount of energy to be stored in the electrostatic field of the capacitor, while the demand for higher performance requires faster charging/discharging in shorter time periods. At present, the capacitance of integrated planar MIS/MIM capacitors is limited to 20 fF/μm2 because of constraints imposed by the available chip area and materials to be used as dielectrics in advanced capacitors. The latter constraints arise from contamination issues present in CMOS technologies which restrict dielectrics used in MIS/MIM capacitors of advanced ICs to be compatible with the CMOS technology. Although, in general, the capacitance of a capacitor may be increased by increasing its surface, decreasing the distance between its electrodes and increasing the dielectric constant or k-value of a dielectric disposed in between the electrodes of a capacitor. However, in advanced ICs, decreasing the distance between the electrodes is limited due to the appearance of leakage currents with decreasing thickness of the dielectric. Therefore, current developments consider increasing the surface of the electrode by means of so-called 3D capacitors in which a dense network of pores is formed in the surface of a semiconductor substrate, the pores being filled with a high-k dielectric material such that higher capacitance densities may be obtained. Still, increasing the capacitance raises another issue which will be described with regard to FIG. 1.
FIG. 1 represents a graphic relation between the charge of a MIS/MIM capacitor plotted on the ordinate and the voltage applied to the capacitor plotted on the abscissa. The MIS/MIM capacitor was formed in accordance with conventional techniques and measured by the inventors. As indicated in FIG. 1, a required high target load of, for example, 15 μC/cm2 involves a high voltage drop across the capacitor, in the given example about 7 V, possibly causing dielectric breakdown and, therefore, posing a risk to the reliability of the whole IC comprising the capacitor.
Conventionally, capacitors with high capacitances are located on or in chip interposers and suitable integrated capacitors showing high capacitances are not available, such that space-consuming external passive components appear to be the only choice at present.
Ferroelectric dielectrics have been recently considered with regard to ferroelectric FETs (FeFETs) in non-volatile memory applications. U.S. Pat. No. 8,304,823 represents an approach in this respect suggesting usage of a hafnium and/or zirconium including ferroelectric material as a gate oxide in FeFETs.
Although ferroelectric and antiferroelectric dielectrics are generally known to have high dielectric constants or k-values, implementations, particularly of antiferroelectric dielectrics, raise new issues when considering concrete applications in advanced semiconductor fabrication. For example, typical antiferroelectric films have a thickness of several 100 nm, and conventional antiferroelectric materials like perovskites, e.g., PZT, BaTiO3 and SBT, are not compatible with semiconductor manufacturing environments as contaminations are introduced, possibly causing yield losses in semiconductor fabrication plants.
It is desirable to provide integrated circuit elements and MIM/MIS capacitors having high capacitances. Furthermore, it is desirable to provide a method of forming an integrated circuit element having a high capacitance and a method of controlling an integrated circuit element and a method of controlling a MIM/MIS capacitor having a high capacitance.